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????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the MAX5316 is a high-accuracy, 16-bit, serial spi input, buffered voltage output digital-to-analog converter (dac) in a 4mm x 5mm, 24-lead tqfn package. the device features q 1 lsb inl (max) accuracy and a q 0.25 lsb dnl (typ) accuracy over the temperature range of -40 n c to +105 n c. the dac voltage output is buffered with a fast set - tling time of 3 f s and a low offset and gain drift of q 0.6ppm/ n c of fsr (typ). the force-sense output (out) maintains accuracy while driving loads with long lead lengths. a separate avss supply pin is provided to per - mit the output amplifier to go to 0v (gnd) to maintain full linearity performance near ground. at power-up, the device resets its outputs to zero or midscale. the wide 2.7v to 5.5v supply voltage range and inte - grated low-drift, low-noise reference buffer make for ease of use. the MAX5316 features a 50mhz 3-wire spi inter - face. for an i 2 c interface, use the max5317. the MAX5316 is available in a 24-lead tqfn-ep pack - age and operates over the -40 n c to +105 n c temperature range. applications test and measurement automatic test equipment gain and offset adjustment data-acquisition systems process control and servo loops programmable voltage and current sources automatic calibration communication systems medical equipment benefits and features s ideal for ate and high-precision instruments ? inl accuracy guaranteed with 1 lsb (max) over temperature s fast settling time (3s) with 10k i || 100pf load s safe power-up-reset to zero or midscale dac output (pin-selectable) ? predetermined output device state in power-up and reset in system design s negative supply (avss) option allows full inl and dnl performance to 0v s spi interface compatible with 1.7v to 5.5v logic s high integration reduces development time and pcb area ? buffered voltage output directly drives 2k i load rail-to-rail ? integrated reference buffer ? no external amplifiers required s small 4mm x 5mm, 24-pin tqfn package 19-6166; rev 0; 1/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX5316.related . qspi is a trademark of motorola, inc. microwire is a registered trademark of texas instrument incorporated. functional diagram 16-bit dac output buffer ref control logic shutdown power-on reset spi interface buffer v ddio dgnd bypass agnd_s agnd_f avss avdd2 avdd1 16 22 19 12 refo rfb out 15 14 13 7.8ki 7.8ki 7.8ki 7.8ki ldac ready sclk din dout cs 3 24 6 5 4 7 agnd 21 20 17 18 10 11 MAX5316 spi busy rst m/ z tc/ sb pd 2 23 1 8 9 input/ dac register MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface agnd to dgnd ................................................... -0.3v to +0.3v agnd_f, agnd_s to agnd ............................... -0.3v to +0.3v agnd_f, agnd_s to dgnd ............................... -0.3v to +0.3v avdd_ to agnd ..................................................... -0.3v to +6v avdd_ to ref ......................................................... -0.3v to +6v avss to agnd ........................................................ -2v to +0.3v v ddio to dgnd ....................................................... -0.3v to +6v bypass to dgnd ....................................... -0.3v to the lower of (v avdd_ or v ddio + 0.3v) and +6v out, refo, rfb to agnd ......................... -0.3v to the lower of (v avdd_ + 0.3v) and +6v ref to agnd .............................................. -0.3v to the lower of v avdd and +6v sclk, din, cs , busy , ldac , ready , m/ z , tc/ sb , rst , pd, dout to dgnd ....... -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70 n c) tqfn (derate 28.6mw/ n c above +70 n c) ............... 2285.7mw operating temperature range ........................ -40 n c to +105 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-case thermal resistance ( q ja ) .............. 1.8c/w junction-to-ambient thermal resistance ( q ja ) .......... 35c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v avdd_ = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units static performance resolution n 16 bits integral nonlinearity (note 3) inl din = 0x0000 to 0xffff (binary mode), din = 0x8000 to 0x7fff (twos complement mode) -1 q 0.25 +1 lsb din = 0x0640 to 0xffff (binary mode), din = 0x8280 to 0x7fff (twos complement mode), v avss = 0v differential nonlinearity (note 3) dnl -1 q 0.25 +1 lsb zero code error oe din = 0, t a = +25 n c -19 q 1 +19 lsb din = 0, t a = -40 n c to +105 n c q 6 zero code error drift din = 0 -2.5 q 0.4 +2.5 ppm/ n c gain error ge t a = +25 n c -4 q 0.25 +4 lsb t a = -40 n c to +105 n c q 3 gain error temperature coefficient tcge -2.75 q 0.6 +2.75 ppm/ n c of fsr
????????????????????????????????????????????????????????????????? maxim integrated products 3 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface electrical characteristics (continued) (v avdd_ = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units output voltage range 0 v avdd - 0.1 v reset voltage output v out-reset rst = pulse low m/ z = dgnd 75 f v m/ z = v ddio 2.048 v rst = pulse low, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 2.048 v rst = dgnd m/ z = dgnd -40 mv m/ z = v ddio 2.037 v rst = dgnd, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 2.037 v dc output impedance (normal mode) r out closed-loop connection (rfb connected to out) 4 m i output resistance (power-down mode) pd = v ddio 2 k i output current i out source/sink within 100mv of the supply rails q 4 ma source/sink within 800mv of the supply rails q 25 load capacitance to gnd c l 200 pf load resistance to gnd r l for specified performance 2 k i short-circuit current i sc out shorted to agnd or avdd q 60 ma refo shorted to agnd or avdd q 65 bypass shorted to agnd or avdd q 48 short-circuit duration t sc short to agnd or avdd indefinite s dc power-supply rejection dc psrr v out at full scale, v avdd = 4.5v to 5.5v -1 q 0.05 +1 lsb/v v avss = -1.5v to -0.5v -1 q 0.003 +1 static performancevoltage reference input section reference high input range v ref 2.4 v avdd - 0.1 v reference input capacitance c ref 10 pf reference input resistance r ref 10 m i reference input current i b q 0.05 f a static performancevoltage reference output section reference high output range 2.4 v avdd - 0.1 v reference high output load regulation 500 ppm/ ma reference output capacitor r esr < 5 i 0.1 0.15 nf
????????????????????????????????????????????????????????????????? maxim integrated products 4 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface electrical characteristics (continued) (v avdd_ = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units static performancev bypass out section output voltage v bypass 2.3 2.4 2.5 v load capacitance to gnd c l required for stability, r esr = 0.1 i (typ) 1 10 f f power-supply requirements positive analog power-supply range v avdd 4.5 5.5 v digital interface power-supply range v ddio 1.7 v avdd v negative analog power-supply range v avss -1.5 -1.25 0 v positive analog power-supply current i avdd no load, external reference, output at zero scale 5.5 7.5 ma negative analog power-supply current i avss no load, external reference, output at zero scale -1.75 -1.0 ma interface power-supply current i vddio digital inputs at v ddio or dgnd 1 10 f a positive analog power-supply power-down current pd = v ddio , power-down mode 20 50 f a negative analog power-supply power-down current pd = v ddio , power-down mode -10 -3 f a dynamic performance voltage output slew rate sr from 10% to 90% full scale, positive and negative transitions 4.9 v/ f s voltage output settling time t s from falling edge of ldac to within 0.003% fs, r l = 10k i , din = 1000h (6.25% fs) to f000h (93.75% fs) 3 f s busy time t busy (note 4) 1.9 f s dac glitch impulse major code transition (1fffh to 8000h), r l = 10k i , c l = 50pf 4 nvs digital feed through csb = v ddio , f sclk = 1khz, all digital inputs from 0v to v ddio 1 nvs output voltage-noise spectral density at f = 1khz to 10khz, without reference noise, code = 8000h 26 nv/ hz output voltage noise at f = 0.1hz to 10hz, without reference noise, code = 8000h 1.55 f v p-p wake-up time from power-down mode 75 f s power-up time from power-off 1 ms
????????????????????????????????????????????????????????????????? maxim integrated products 5 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface electrical characteristics (v avdd_ = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units static performance resolution n 16 bits integral nonlinearity (note 3) inl din = 0x0000 to 0xffff (binary mode), din = 0x8000 to 0x7fff (twos complement mode) -1.0 q 0.20 +1.0 lsb din = 0x0640 to 0xffff (binary mode), din = 0x8280 to 0x7fff (twos complement mode), v avss = 0v differential nonlinearity ( note 3) dnl -1.0 q 0.10 +1.0 lsb zero code error oe din = 0, t a = +25 n c -20 +1.5 +20 lsb din = 0, t a = -40 n c to +105 n c q 4 zero code error drift (note 2) din = 0 -3 q 0.35 +3 ppm/ n c gain error ge t a = +25 n c -4 q 0.65 +4 lsb t a = -40 n c to +105 n c q 3 gain error temperature coefficient (note 2) tcge -3 +3 ppm/ n c of fsr output voltage range 0 v avdd - 0.1 v reset voltage output v out- reset rst = pulse low m/ z = dgnd 75 f v m/ z = v ddio 1.25 v rst = pulse low, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 1.25 v rst = dgnd m/ z = dgnd -40 mv m/ z = v ddio 1.25 v rst = dgnd, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 1.24 v dc output impedance r out closed-loop connection, rfb connected to out 4 m i output current i out source/sink within 100mv of the supply rails q 4 ma source/sink within 800mv of the supply rails q 25 load capacitance to gnd c l 200 pf load resistance to gnd r l for specified performance 2 k i short-circuit current isc out shorted to agnd or avdd q 60 ma refo shorted to agnd or avdd q 65 bypass shorted to agnd or avdd q 48 short-circuit duration tsc short to agnd or avdd indefinite s dc power-supply rejection dcpsrr v out at full scale, v avdd = 2.7v to 3.3v -1 q 0.1 +1 lsb/v v avss = -1.5v to -0.5v -1 q 0.01 +1
????????????????????????????????????????????????????????????????? maxim integrated products 6 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface electrical characteristics (continued) (v avdd_ = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units static performancevoltage reference input section reference high input range v ref 2.4 v avdd - 0.1 v reference input capacitance c ref 10 pf reference input resistance r ref 10 m i reference input current ib q 0.05 f a static performancevoltage reference output section reference high output range 2.4 v avdd - 0.1 v reference high output load regulation 500 ppm/ma reference output capacitor r esr < 5 i 0.1 0.15 nf static performancev bypass out section output voltage v bypass 2.3 2.4 2.5 v load capacitance to gnd c l required for stability, r esr = 0.1 i (typ) 1 10 f f power-supply requirements positive analog power-supply range v avdd 2.7 3.3 v interface power-supply range v ddio 1.7 v avdd v negative analog power-supply range v avss -1.5 -1.25 0 v positive analog power-supply current i avdd no load, external reference, output at zero scale 4 6.5 ma negative analog power-supply current i avss no load, external reference, output at zero scale -1.5 -0.8 ma interface power-supply current i vddio digital inputs at v ddio or dgnd 1 10 f a positive analog power-supply power-down current pd = v ddio , power-down mode 20 50 f a negative analog power-supply power-down current pd = v ddio , power-down mode -10 -3 f a dynamic performance voltage output slew rate sr from 10% to 90% full scale, positive and negative transitions 4.9 v/ f s voltage output settling time t s from falling edge of ldac to within 0.003% fs, r l = 10k i , din = 1000h (6.25% fs) to f000h (93.75% fs) 3 f s
????????????????????????????????????????????????????????????????? maxim integrated products 7 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface electrical characteristics (continued) (v avdd_ = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) note 2: all devices are 100% tested at t a = +25 c and t a = + 105 c . limits at t a = -40 c are guaranteed by design. note 3: linearity is tested from v refo to agnd. note 4: the total analog throughput time from din to v out is the sum of t s and t busy (4.9s, typ). digital interface electrical characteristics (v avdd_ = 5v, v ddio = 2.7v to 5.5v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z , c refo = 100pf, c l = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units busy time t busy (note 4) 1.9 f s dac glitch impulse major code transition (7fffh to 8000h), r l = 10k i , c l = 50pf 2.5 nvs digital feedthrough csb = v ddio , f sclk = 1khz, all digital inputs from 0v to v ddio 1 nvs output voltage-noise spectral density at f = 1khz to 10khz, without reference noise, code = 8000h 26 nv/ hz output voltage noise at f = 0.1hz to 10hz, without reference noise, code = 8000h 1.55 f v p-p wake-up time from power-down mode 75 f s power-up time from power-off 1 ms parameter symbol conditions min typ max units digital inputs (sclk, din, cs , ldac ) input high voltage v ih 0.7 x v ddio v input low voltage v il 0.3 x v ddio v input hysteresis v ihyst 200 300 mv input leakage current i in input = 0v of v ddio q 0.1 q 1 f a input capacitance c in 10 pf digital output characteristics (dout, ready , busy ) output low voltage v ol i source = 5.0ma 0.25 v output high voltage v oh i sink = 5.0ma, except for busy v ddio - 0.25 output three-state leakage i oz dout only q 0.1 q 1 f a output three-state capacitance c oz dout only 15 pf output short-circuit current i oss v ddio = 5.5v q 150 ma
????????????????????????????????????????????????????????????????? maxim integrated products 8 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface digital interface electrical characteristics (continued) (v avdd_ = 5v, v ddio = 2.7v to 5.5v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z , c refo = 100pf, c l = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units timing characteristics serial clock frequency f sclk stand-alone, write mode 50 mhz stand-alone read mode and daisy- chained read and write modes (note 5) 12.5 sclk period t cp stand-alone, write mode 20 ns stand-alone read mode and daisy- chained read and write modes 80 sclk pulse width high t ch 40% duty cycle 8 ns sclk pulse width low t cl 40% duty cycle 8 ns cs fall to sclk fall setup time t csso first sclk falling edge stand-alone, write mode 8 ns stand-alone read mode and daisy- chained read and write modes 28 cs fall to sclk fall hold time t csh0 inactive falling edge preceding first falling edge 0 ns sclk fall to cs rise hold time t csh1 24th falling edge 2 ns din to sclk fall setup time t ds 5 ns din to sclk fall hold time t dh 4.5 ns sclk rise to dout settle time t dot c l = 20pf (note 6) 32 ns sclk rise to dout hold time t doh c l = 0pf (note 6) 2 ns sclk fall to dout disable time t doz 24th active edge deassertion 2 30 ns cs fall to dout enable t doe asynchronous assertion 2 30 ns cs rise to dout disable t csdoz stand-alone, aborted sequence 35 ns daisy-chained, aborted sequence 20 sclk fall to ready fall t crf 24th falling-edge assertion, c l = 20pf 30 ns sclk fall to ready hold t crh 24th falling-edge assertion, c l = 0pf 2 ns sclk fall to busy fall t cbf busy assertion 5 ns cs rise to ready rise t csr c l = 20pf 35 ns cs rise to sclk fall t csa 24th falling edge, aborted sequence 20 ns cs pulse width high t cspw stand alone 20 ns sclk fall to cs fall t csf 24th falling edge 100 ns ldac pulse width t ldpw 20 ns ldac fall to sclk fall hold t ldh last active falling edge 20 ns rst pulse width t rstpw 20 ns
????????????????????????????????????????????????????????????????? maxim integrated products 9 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface digital interface electrical characteristics (continued) (v avdd_ = 5v, v ddio = 1.8v to 2.7v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z , c refo = 100pf, c l = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units digital inputs (sclk, din, cs , ldac ) input high voltage v ih 0.8 x v ddio v input low voltage v il 0.2 x v ddio v input hysteresis v ihyst 200 300 mv input leakage current i in input = 0v or v ddio q 0.1 q 1 f a input capacitance c in 10 pf digital output characteristics (dout, ready , busy ) output low voltage v ol i source = 1.0ma 0.2 v output high voltage v oh i sink = 1.0ma, except for busy v ddio - 0.2 v output three-state leakage i oz dout only q 0.1 q 1 f a output three-state capacitance c oz dout only 15 pf output short-circuit current i oss v ddio = 2.7v q 150 ma timing characteristics serial clock frequency f sclk stand-alone, write mode 50 mhz stand-alone read mode and daisy chained read and write modes (note 5) 8 sclk period t cp stand-alone, write mode 20 ns stand-alone read mode and daisy- chained read and write modes 125 sclk pulse width high t ch 40% duty cycle 12 ns sclk pulse width low t cl 40% duty cycle 12 ns cs fall to sclk fall setup time t csso first sclk falling edge stand-alone, read mode 12 ns stand-alone read mode and daisy-chained read and write modes 36 cs fall to sclk fall hold time t csh0 inactive falling edge preceding first falling edge 0 ns sclk fall to cs rise hold time t csh1 24th falling edge 4 ns din to sclk fall setup time t ds 8 ns din to sclk fall hold time t dh 8 ns
???????????????????????????????????????????????????????????????? maxim integrated products 10 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface digital interface electrical characteristics (continued) (v avdd_ = 5v, v ddio = 1.8v to 2.7v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z , c refo = 100pf, c l = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) note 5: daisy-chain speed is relaxed to accommodate (t crf + t css0 ). note 6: dout speed limits overall spi speed. 50mhz is only specified without dout functionality. parameter symbol conditions min typ max units sclk rise to dout settle time t dot c l = 20pf (note 6) 60 ns sclk rise to dout hold time t doh c l = 0pf (note 6) 2 ns sclk fall to dout disable time t doz 24th active edge deassertion 2 40 ns cs fall to dout enable t doe asynchronous assertion 2 50 ns cs rise to dout disable t csdoz stand-alone, aborted sequence 70 ns daisy-chained, aborted sequence 130 sclk fall to ready fall t crf 24th falling edge assertion, c l = 20pf 60 ns sclk fall to ready hold t crh 24th falling edge assertion, c l = 0pf 2 ns sclk fall to busy fall t cbf busy assertion 5 ns cs rise to ready rise t csr c l = 20pf 60 ns cs rise to sclk fall t csa 24th falling edge, aborted sequence 20 ns cs pulse width high t cspw stand alone 20 ns sclk fall to cs fall t csf 24th falling edge 100 ns ldac pulse width t ldpw 20 ns ldac fall to sclk fall hold t ldh last active falling edge 20 ns rst pulse width t rstpw 20 ns
???????????????????????????????????????????????????????????????? maxim integrated products 11 figure 1. serial interface timing diagram, stand-alone operation typical operating characteristics (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) r3 12 t csso 34 56 78 21 22 23 24 25 din sclk t csh0 r2 r1 r0 d17 d16 d15 d14 d1 d0 x ?? 0r 3 r2 r1 r0 d17 d16 d15 d2 d1 d0 0 z dout cs z t csh1 t csa t ds t dh t cp t cl t ch t doh t dot t doe t cspw t doz t crh t csf t crf t csr ready differential nonlinearity vs. digital input code MAX5316 toc01 code dnl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 2.5v v avdd = 3v integral nonlinearity vs. digital input code MAX5316 toc02 code inl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 2.5v v avdd = 3v MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 12 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) differential nonlinearity vs. digital input code MAX5316 toc03 code dnl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 4.096v v avdd = 5v integral nonlinearity vs. digital input code MAX5316 toc04 code inl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 4.096v v avdd = 5v differential nonlinearity vs. digital input code MAX5316 toc05 code dnl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 5v v avdd = 5.25v integral nonlinearity vs. digital input code MAX5316 toc06 code inl (lsb) 49152 65536 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 v ref = 5v v avdd = 5.25v temperature (c) 95 80 50 65 -10 5 20 35 -25 110 differential nonlinearity vs. temperature MAX5316 toc07 dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 v ref = 2.5v min dnl max dnl temperature (c) 95 80 50 65 -10 5 20 35 -25 110 integral nonlinearity vs. temperature MAX5316 toc08 inl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 v ref = 2.5v min inl max inl MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 13 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v avdd (v) integral nonlinearity vs. supply voltage MAX5316 toc12 inl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v ref = 2.5v min inl max inl 4.8 4.4 3.6 4.0 3.2 2.8 2.4 5.2 reference voltage (v) differential nonlinearity vs. reference voltage MAX5316 toc13 dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v avdd = 5.25v min dnl max dnl 4.8 4.4 3.6 4.0 3.2 2.8 2.4 5.2 reference voltage (v) integral nonlinearity vs. reference voltage MAX5316 toc14 inl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v avdd = 5.25v min inl max inl temperature (c) 95 80 50 65 -10 5 20 35 -25 110 differential nonlinearity vs. temperature MAX5316 toc09 dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 v ref = 4.096v min dnl max dnl temperature (c) 95 80 50 65 -10 5 20 35 -25 110 integral nonlinearity vs. temperature MAX5316 toc10 inl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 min inl max inl v ref = 4.096v 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v avdd (v) differential nonlinearity vs. supply voltage MAX5316 toc11 dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v ref = 2.5v min dnl max dnl MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 14 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) zero-scale output error vs. supply voltage MAX5316 toc15 output error (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v ref = 2.5v code = 0x0000 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v avdd (v) full-scale output error vs. supply voltage MAX5316 toc16 output error (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 v ref = 2.5v code = 0xffff 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v avdd (v) zero-scale output error vs. output current MAX5316 toc17 output current (ma) output error (lsb) 27 24 18 21 6 9 12 15 3 03 0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 code = 0x0000 v avss = -1.25v v ref = 4.096v sinking sourcing full-scale output error vs. output current MAX5316 toc18 output current (ma) output error (lsb) 27 24 18 21 6 9 12 15 3 03 0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 code = 0xffff v ref = 4.096v sinking sourcing output drive capability MAX5316 toc19 output current (ma) output error (lsb) 7 6 4 5 2 3 1 -8 -6 -4 -2 0 2 4 6 8 10 -10 08 code = 0x0640 v avss = 0v v ref = 4.096v sinking current t a = +25c output drive capability MAX5316 toc20 output current (ma) output error (lsb) 7 6 4 5 2 3 1 -8 -6 -4 -2 0 2 4 6 8 10 -10 08 code = 0xffff v avdd = 4.2v v ref = 4.096v sourcing current t a = +25c MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 15 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 45 40 30 35 10 15 20 25 5 output drive capability MAX5316 toc21 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0x0000 v avss = -1.25v v ref = 4.096v sinking current t a = +25c 45 40 30 35 10 15 20 25 5 output drive capability MAX5316 toc22 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0xffff v avdd = 5v v ref = 4.096v sourcing current t a = +25c 45 40 30 35 10 15 20 25 5 output drive capability MAX5316 toc23 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0x0000 v avss = -1.25v v ref = 2.5v sinking current t a = +25c 55 50 45 40 30 35 10 15 20 25 5 output drive capability MAX5316 toc24 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 06 0 code = 0xffff v avdd = 5v v ref = 2.5v sourcing current t a = +25c supply current vs. supply voltage MAX5316 toc25 v avdd (v) i avdd (ma) 5.25 5.00 4.75 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 5.0 4.50 5.50 t a = +25c t a = -40c t a = +105c v ref = 4.096v 15 20 25 30 35 power-down supply current vs. supply voltage MAX5316 toc26 v avdd (v) i avdd (a) 5.25 5.00 4.75 40 10 4.50 5.50 t a = +25c t a = -40c t a = +105c v pd = v ddio v ref = 4.096v MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 16 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 100 200 300 400 500 ground current vs. code MAX5316 toc27 code current (a) 49152 65536 32768 16384 600 0 0 current out of agnd_f and agnd_s v ref = 4.096v 0.1hz to 10hz output noise MAX5316 toc29 v out 1v/div 1s / div 10k 1k 100 10 100k output noise density MAX5316 toc28 frequency (hz) voltage noise (nv/hz) 10 20 30 40 50 60 70 80 90 100 0 code = 0x8000 major carry glitch (1 lsb negative step) MAX5316 toc30 v ldac 5v/div v out 10m v/div 400ns / div major carry glitch (1 lsb positive step) MAX5316 toc31 400ns / div v ldac 5v/div v out 10m v/div settling time (code = 0x1000 to 0xf000) MAX5316 toc32 1s / div v ldac 5v/div v out 2v/div v out 200v/div settling time (code = 0xf000 to 0x1000) MAX5316 toc33 1s / div v ldac 5v/div v out 2v/div v out 200v/div MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 17 typical operating characteristics (continued) (v avdd_ = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) digital clock feedthrough MAX5316 toc34 v sclk 5v/div v out 1mv/div 2s / div exiting power-down response MAX5316 toc36 v pd 1v/div v out 2v/div 10s / div entering power-down response MAX5316 toc35 v pd 1v/div v out 2v/div 10s / div slow power-up response (rstsel = low) MAX5316 toc37 v avdd 5v/div v avss 2v/div v refo 2v/div v bypass 2v/div v out 2v/div 4ms / div slow power-up response (rstsel = high) MAX5316 toc38 v avdd 5v/div v avss 2v/div v refo 2v/div v bypass 2v/div v out 2v/div 4ms / div MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface
???????????????????????????????????????????????????????????????? maxim integrated products 18 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface pin description pin configuration tqfn *exposed pad-connect to agnd. top view MAX5316 1 m/ z 2 3 4 dout 5 din 6 sclk 7 cs *ep 19 avdd2 18 agnd_f 17 agnd_s 16 ref 15 refo rst v ddio dgnd bypass 14 rfb 13 out 8 tc/sb 9 pd 10 avss 11 agnd 12 avdd1 24 23 22 21 20 + busy ldac ready pin name function 1 m/ z reset select input. m/ z selects the default state of the analog output (out) after power-on or hardware or software reset. connect m/ z to v ddio to set the default output voltage to midscale or to dgnd to set the default output voltage to zero scale. 2 busy digital input/open-drain output. connect a 5.1k i pullup resistor from busy to v ddio . busy goes low immediately after writing to the din register. during this time, the user can continue writing new data to the din register, but no further updates to the dac register and dac output can take place. if ldac is asserted low while busy is low, this event is stored. busy is bidirectional, and can be asserted low externally to delay ldac action. busy also goes low during power-on reset, when rst is low, or when software reset is activated. 3 ldac active-low load dac logic input. if ldac is taken low while busy is inactive (high), the contents of the input registers are transferred to the dac register and the dac output is updated. if ldac is taken low while busy is asserted low, the ldac event is stored and the dac register update is delayed until busy deasserts. any event on ldac during power-on reset or when rst is low is ignored. 4 dout spi bus serial data output. see the serial interface section for details.
???????????????????????????????????????????????????????????????? maxim integrated products 19 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface pin description (continued) pin name function 5 din spi bus serial data input. see the serial interface section for details. 6 sclk spi bus serial clock input. see the serial interface section for details. 7 cs spi bus active-low chip-select input. see the serial interface section for details. 8 tc/ sb din format select input. connect tc/ sb to dgnd to set the data input format to straight binary or to vddio to set it to twos complement. 9 pd active-high power-down input. connect pd to dgnd for normal operation. connect pd to vddio to place the device in power-down. in power-down, out (analog voltage output) is connected to agnd through a 2k resistor, but the contents of the input registers and the dac latch do not change. the spi interface remains active in power-down. 10 avss negative analog power-supply input. connect to agnd or a negative supply voltage. when connected to the negative supply voltage, bypass avss with a 0.1f capacitor to agnd. 11 agnd analog ground. connect to the analog ground plane. 12, 19 avdd1 positive analog power-supply input. bypass each avdd_ locally with a 0.1f and 10f capacitor to agnd (analog ground plane). connect avdd1 and avdd2 together. 13 out buffered analog voltage output. connect out to rfb externally to close the output buffer feedback loop. the buffered output is capable of directly driving a 10k load. the state of m/ z sets the power-on reset state of out (zero or midscale). in power-down, out is connected to agnd through a 2k pulldown resistor. 14 rfb feedback resistor input. rfb is connected through the internal feedback resistor to the inverting input of the analog output buffer. externally connect rfb to out to close the output buffer feedback loop. 15 refo voltage reference buffered output. bypass with a 100pf capacitor to agnd. 16 ref high-impedance 10m voltage reference input 17 agnd_s dac analog ground sense 18 agnd_f dac analog ground force. connect to the analog ground plane. 19 avdd2 positive analog power-supply input. avdd2 supplies power to the internal digital linear regulator. bypass avdd2 locally to agnd with 0.1f and 10f capacitors. connect avdd2 and avdd1 together. 20 bypass internal bypass connection. connect bypass to dgnd with 0.01f and 1f capacitors. 21 dgnd digital ground 22 v ddio digital interface power-supply input. connect to a 1.7v to 5.5v logic-level supply. bypass v ddio with a 0.1f capacitor to dgnd. the supply voltage at v ddio sets the logic-level for the digital interface. 23 rst active-low reset input. drive rst low to dgnd to put the device into a reset state. a reset state sets all spi input registers to their default power-on reset states as defined by the state of inputs m/ z and tc/ sb . set rst high to v ddio , the dac output remains at the state defined by m/ z until ldac is taken low. 24 ready spi active-low ready output. ready asserts low when the device successfully completes processing an spi data frame. ready asserts high at the next rising edge of cs . in daisy-chain applications, the ready output typically drives the cs input of the next device in the chain or a gpio of a microcontroller. ep exposed pad. ep is internally connected to agnd. connect to the analog ground plane.
???????????????????????????????????????????????????????????????? maxim integrated products 20 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface detailed description the MAX5316 is a high-accuracy, 16-bit, serial spi input, buffered voltage output digital-to-analog converter (dac) in a 4mm x 5mm, 24-lead tqfn package. the device features q 1 lsb inl (max) accuracy and a q 1 lsb dnl (max) accu - racy over the -40 n c to +105 n c temperature range. the dac voltage output is buffered with a fast set - tling time of 3 f s and a low offset and gain drift of q 0.6ppm/ n c of fsr (typ). the force-sense output (out) maintains accuracy while driving loads with long lead lengths. a separate avss supply allows the output amplifier to go to 0v (gnd) while maintaining full linearity performance. at power-up, the device resets its outputs to zero or mid - scale, providing additional safety for applications which drive valves or other transducers that need to be off on power-up. this is selected by the state of the m/ z input on power-up. the wide supply voltage range of 2.7v to 5.5v and integrated low-drift, low-noise reference buffer ampli - fier makes for ease of use. since the reference buffer input has a high input resistance, an external buffer is not required. the device accepts an external reference between 2.4v and v avdd - 0.1v for maximum flexibility. the MAX5316 features a 50mhz, 3-wire spi, qspi, microwire, and dsp-compatible serial interface. the separate digital interface supply voltage input (v ddio ) is compatible with a wide range of digital logic levels from 1.7v to 5.5v, eliminating the need for separate voltage translators. dac reference buffer the external reference input has a high input (ref) imped - ance of 10m i || 10pf and accepts an input voltage from +2.4v to v avdd - 0.1v. connect an external reference supply between ref and agnd. bypass the reference buffer output refo to agnd with a 100pf capacitor. connect the anode of an external schottky diode to ref and the cathode to avdd1 to prevent internal esd diode conduction in the event that the reference voltage comes up before avdd at power up. follow the recommenda - tions described in the power-supply sequencing section. visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. output amplifier (out) the MAX5316 includes an internal buffer for the dac output. the internal buffer provides improved load regulation for the dac output. the output buffer slews at 5v/ f s and can drive up to 2k i in parallel with 200pf. the buffer has a rail-to-rail output capable of swinging to within 100mv of avdd_ and avss. the positive analog supply voltage (avdd_) determines the maximum output voltage of the device as avdd_ powers the output buffer. the output is diode clamped to ground, preventing nega - tive voltage excursions beyond approximately -0.6v. negative supply voltage (avss) the negative supply voltage (avss) determines the minmum output voltage. if avss is connected to ground, the output voltage can be set to as low as 100mv without degrading linearity. for operation down to 0v, connect avss to a nega - tive supply voltage between -0.1v and -1.25v. the max1735 is recommended for generating -1.25v from a -5v supply. force/sense the MAX5316 uses force/sense techniques to ensure that the load is regulated to the desired output volt - age despite line drops due to long lead lengths. since agnd_f and agnd_s have code dependent ground currents, a ground impedance less than 13m ensures that the inl will not degrade by more than 0.1 lsb. form a star ground connection ( figure 2a ) near the device with agnd_f, agnd_s, and agnd tied together. always refer remote dac loads to this system ground for best performance. figure 2b shows how to configure the device and an external op amp for proper force/sense operation. the amplifier provides as much drive as needed to force the sensed voltage (measured between rfb and agnd_s) to equal the desired voltage. figure 2a. star ground connection figure 2b. force/sense connection out rfb agnd_f agnd_s agnd MAX5316 out rfb agnd agnd_f agnd_s MAX5316
???????????????????????????????????????????????????????????????? maxim integrated products 21 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface 16-bit ideal transfer function the transfer function for the MAX5316 is given by: out ref 16 code vv 2 (din code from 0x0000 to 0xffff) = for the simple binary case and: out ref 16 ref out ref 16 (code 0x8000) vv 2 (din code from 0x8000 to 0xffff) v code vv 2 2 (din code from 0x0000 to 0xffff) ? = =+ for the twos complement case. straight binary vs. twos complement table 1 and table 2 show the math necessary to convert the din code into v out for the 16-bit dac. 1 lsb is equal to v ref /2 16 . input range the range of din is summarized in table 3 and table 4 . also shown are the range values for the MAX5316 with a 4.096v reference. note that v ref is the reference voltage applied to ref and 1 lsb is equal to v ref /2 16 . table 3. din range (straight binary mode) table 4. din range (twos complement mode) figure 3. din to v out transfer curve din v out v ref 0v 0x0000 0x8000 0x8000 0x0000 0xffff straight binary 0x7fff two?s complement zero-scale midscale full-scale v ref /2 range din code v out (v) MAX5316 value (v) minimum 0x0000 0 0 maximum 0xffff (v ref - 1 lsb) 4.095938 range din code v out (v) MAX5316 value (v) minimum 0x8000 0 0 maximum 0x7fff (v ref - 1 lsb) 4.095938 table 1. straight binary mode din code equation for v out range 0x0000 to 0xffff 0v to (v ref - 1 lsb) out ref 16 code vv 2 = table 2. twos complement mode din code equation for v out range 0x8000 to 0xffff 0v to (v ref /2 -1 lsb) 0x0000 to 0x7fff v ref /2 to (v ref - 1 lsb) ref out ref 16 v code vv 2 2 =+ out ref 16 code 0x8000 vv 2 ? ?? = ?? ??
???????????????????????????????????????????????????????????????? maxim integrated products 22 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface reset the device is reset upon power-on, hardware reset using rst , or software reset using register 0x4, bit 15, com - mand rstsw . after reset, the value of the input register, the dac latch and the output voltage are set to the values defined by the m /z input. if a hardware reset occurs dur - ing a spi programming frame, anything before and after the reset for the frame will be ignored. a software reset initiated through the spi interface takes effect after the end of the valid frame. output state upon reset the output voltage can be set to either zero or mid - scale upon power-up, or a hardware or software reset, depending on the state of the m/ z input. after power-up, if the device detects that this input is low, the output volt - age is set to zero scale. if m/ z is high, the output voltage is set to midscale. note that during reset, when rst is low or rstsw is set to 0, the output voltage is set slightly lower than the value after coming out of reset. during reset, the output voltage is set to the values shown for the v out-reset specifica - tion in the electrical characteristics . power-down the device can be powered down by either hardware (pulling pd high) or software (setting the pd_sw bit in either the 0x4 or 0xc registers). note that the hardware and software inputs are ored. asserting either is enough to place the device in power-down mode. in order to restore normal operation to the device, satisfy both of these conditions: 1) pull pd low. 2) set the bits pd_sws (in both 0x4 and 0xc registers) to 0. in power-down, the output is internally connected to agnd through a 2k i resistor. the spi interface remains active and the dac register content remains unchanged. data format selection (straight binary vs. twos complement) the MAX5316 interprets the data code input (din) as either straight binary or twos complement. to choose the straight binary format, set the tc/ sb input low. for twos complement, set the input high. ldac and busy interaction the busy line is open drain and is normally pulled up by an external resistor. it is software-configurable to be bidi - rectional and can be pulled down externally. whenever the din register is changed, the device transfers the value to the dac register. to indicate to the host proces - sor that the device is busy transferring, the device pulls the busy output low. once transfer is complete, the device releases busy and the host processor can load the dac by toggling the ldac input. if ldac is set low while busy is low, the ldac event is latched and imple - mented when the transfer is complete and busy rises. there are four ways in which the ldac and busy out - puts can be used. this is shown graphically in figure 4 . 1) the host sends a new command. the device sets busy low. the host monitors busy to determine when it goes high. the device then pulses ldac low to update the dac. 2) the host sends a new command. the device sets busy low. the host toggles ldac low then high before busy goes high. the device latches the ldac event but does not implement it until processing is complete. then, busy goes high and the device updates the dac. 3) ldac is held low. the host sends a new command and the device sets busy low. the device updates the dac when the processing is complete and busy goes high. 4) busy is pulled down externally to delay dac update. the busy pin is bidirectional. to use busy as an input, set the no_busy bit to 1 using the 0x4 or 0xc command. when configured as an input, pulling busy low at least 50ns before the device releases the line delays dac update. dac update occurs only after busy is released and goes high. if used as an input, drive busy with an open-drain output with a pullup to v ddio . if the dac must be updated at a precise time with the least amount of jitter, use option 1.
???????????????????????????????????????????????????????????????? maxim integrated products 23 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface serial interface overview the spi interface supports speeds up to 50mhz. when cs is high, the remaining interface inputs are disabled to reduce transient currents. the interface supports daisy chaining to enable multiple device to be controlled on the same spi bus. the device has a double-buffered interface consisting of two register banks: the input register and the dac reg - ister. the input register for din is connected directly to the 24-bit spi input shift register. the dac latch contains the dac code and is loaded as defined in the ldac and busy interaction section. a valid spi frame is 24-bit wide with 4-bit command r3 to r0, 16-bit data d15 to d0, and 4 unused lsbs. a full 24-bit spi command sequence is required for all spi command operations, regardless of the number of data bits actually used for the command. any commands terminating with less than a full 24-bit sequence will be aborted without impacting the operation of the part (sub - ject to t csa timing requirements). data is not written into the spi input register or dac and it continues to hold the preceding valid data. if a command sequence with more than 24 bits is provided, the command will be executed on the 24th sclk falling edge and the remainder of the command will be ignored. all spi commands result in the device assuming con - trol of the dout line from the first sclk edge through the 24th sclk edge. after relinquishing the dout line, the MAX5316 will return to a high-impedance state. an optional bus hold circuit can be engaged to hold dout at its last bit value while not interfering with other devices on the bus. dout is disabled at power-up and must be enabled through the spi interface. when enabled, dout echoes the 4-bit command plus 16-bit data, which is being programmed. during readback, dout echoes the 4-bit command followed by the true readback data depending upon the type of read command. table 11 shows the bit positions for dout and din within the 24-bit spi frame. the device is designed such that sclk idles low, and din and dout change on the rising clock edge and get latched on the falling clock edge. the spi host controller should be set accordingly. figure 4. busy and ldac timing din sclk busy busy ldac ldac ldac ldac v out v out v out v out option 1 input register loaded option 2 option 3 option 4 (used as input) x1 2x 21 22 23 x t busy t s t cbf t ldh 50ns t ldpw busy pulled low externally
???????????????????????????????????????????????????????????????? maxim integrated products 24 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface daisy-chain spi operation using ready output the ready pulse appears 24 clock cycles after the neg - ative edge of cs as shown in figure 5 and can therefore be used as the cs line for the next device in the daisy chain. since the device looks at the first 24 bits of the transmission following the falling edge of cs , it is pos - sible to daisy-chain the device with different command word lengths. ready goes high after cs is driven high. to perform a daisy-chain write operation, drive cs low and output the data serially to din. the propagation of the ready signal then controls how the data is read by the device. as the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective cs input. to update just one device in a daisy chain, send the no-op command to the other device in the chain. to update the first device in the chain, raise the cs input after writing to that device. because daisy-chain operation requires paralleling the douts of all the MAX5316 in the chain, the no_holden bit in register 0x4 or 0xc should be set to 1 for all devices. doing so ensures that dout goes into high-impedance after the spi frame is complete (i.e. after the 24th clock cycle) as shown in figure 6 . note that x is dont care. table 5. spi command and data mapping with clock falling edges figure 5. daisy-chain spi connection terminating with a standard spi device c slave 1 sclk din dout mosi miso i/ o sck slave 3 sclk din pout slave 2 sclk din dout cs ready cs ready cs ready clock edge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 din r3 r2 r1 r0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x dout 0 r3 r2 r1 r0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x
???????????????????????????????????????????????????????????????? maxim integrated products 25 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface figure 6. daisy-chain spi connection timing figure 7. stand-alone operation stand-alone operation the diagram in figure 7 shows a stand-alone connec - tion of the MAX5316 in a typical spi application. if more than one peripheral device shares the dout bus, the no_holden bit in register 0x4 or 0xc should be set to 1 for the MAX5316. doing so ensures that dout goes into high-impedance after the spi frame is complete (i.e. after the 24th clock cycle). command and register map all command and data registers have read and write functionality. the register selected depends on the com - mand select bits r[3:0]. each write to the device consists of 4 command select bits (r[3:0]), 16 data bits (which are detailed in tables 7 C 11 ), and 4 dont care lsbs. a sum - mary of the commands is shown in table 6 . cs din dout1 sclk 12 32 4 22 21 20 4 3 21 23 24 22 21 5 4 3 21 23 24 22 21 5 4 3 2 slave 1 data slave 2 data slave 3 data ready 1 ready 3 ready 2 dout2 hi-z hi-z hi-z hi-z dout3 csm cs1 cs cs sclk c dwrite dread sclk din dout MAX5316 to other devices/ chains
???????????????????????????????????????????????????????????????? maxim integrated products 26 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface table 6. register map summary table 7. no-op command (0x0) table 8a. straight binary din write register (tc/ sb ) = 0) (0x1) register details hex r3 r2 r1 r0 function 0 0 0 0 0 no-op. used mainly in daisy-chain communications. 1 0 0 0 1 din register write 2, 3, 5C8, a, b, dCf reserved 4 0 1 0 0 configuration register write 9 1 0 0 1 din register read c 1 1 0 0 configuration and status register read. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x x x x x x x x x x x x x x x x default x x x x x x x x x x x x x x x x bit name description 15:0 dont care no action on spi shift register and dac input registers. use for daisy-chain purposes when r[3:0] = 0000. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x0000 when m z = dgnd (zero scale) 0x8000 when m z = v ddio (midscale) bit name description 15:0 b[15:0] 16-bit dac input code in straight binary format. for clarity, a few examples are shown below. 0000 0000 0000 0000 0x0000 zero scale 0100 0000 0000 0000 0x4000 quarter scale 1000 0000 0000 0000 0x8000 midscale 1100 0000 0000 0000 0xc000 three-quarter scale 1111 1111 1111 1111 0xffff full scale - 1 lsb
???????????????????????????????????????????????????????????????? maxim integrated products 27 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface table 8b. twos complement din write register (tc/ sb ) = 1) (0x1) table 9. general configuration write register (0x4) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x8000 when m z = dgnd (zero scale) 0x0000 when m z = v ddio (midscale) bit name description 15:0 b[15:0] 16-bit dac input code in twos complement format. for clarity, a few examples are shown below. 1000 0000 0000 0000 0x8000 zero scale 1100 0000 0000 0000 0xc000 quarter scale 1111 1111 1111 1111 0xffff midscale C 1 lsb 0000 0000 0000 0000 0x0000 midscale 0000 0000 0000 0001 0x0001 midscale + 1 lsb 0100 0000 0000 0000 0x4000 three-quarter scale 0111 1111 1111 1111 0x7fff full scale C 1 lsb bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pd_sw no_holden rst_sw no_busy dout_on x x x x x x x x x x x default 0 0 1 0 0 x x x x x x x x x x x bit name description 15 pd_sw software pd (power-down). equivalent to the pd input. 0: normal mode 1: power-down mode. out is internally connected to agnd using a 2k i resistor. 14 no_holden spi bus hold enable. 0: bus hold enabled for spi dout output. dout stays at its last value after the spi cs input rises at the end of the spi frame (i.e. after the 24th clock cycle). 1: bus hold disabled for spi dout output. dout goes high impedance after the spi cs input rises at the end of the spi frame (i.e. after the 24th clock cycle). 13 rst_sw software reset. equivalent to the rst input. 0: place device in reset 1: normal operation set the active low rst_sw bit low to initiate a software reset (equivalent to pulling rst low) 12 no_busy busy input disable. 0: busy input is active. 1: busy input is disabled. note that this does not affect the busy bit in the general configuration and status register. the busy pin is bidirectional. when enabled, it can be pulled down externally to delay dac updates. 11 dout_on spi dout output disable. dout is disabled by default. 0: dout output disabled. when dout is disabled, the output is pulled low for the duration of the spi frame. 1: dout output enabled. 10:0 dont care. these bits are reserved for the corresponding read command.
???????????????????????????????????????????????????????????????? maxim integrated products 28 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface table 10. din read register (0x9) table 11. general configuration and status read register (0xc) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name description 15:0 b[15:0] 16-bit din readback value stored in the bits b[15:0]. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pd_sw no_ holden rst_sw no_busy dout_on busy x x x x x x rev_id[3:0] default 0 0 1 0 0 0 0 0 0 0 0 0 0001 bit name description 15 pd_sw software pd (power-down). equivalent to the pd input. 0: normal mode. 1: power-down mode. out is internally connected to agnd using a 2k i resistor. 14 no_holden spi bus hold enable. 0: bus hold enabled for spi dout output. dout stays at its final value after the spi cs input rises at the end of the spi frame. 1: bus hold disabled for spi dout output. dout goes high impedance after the spi cs input rises at the end of the spi frame. 13 rst_sw software reset. equivalent to the rst input. 0: place device in reset. 1: normal operation. set the active low rst_sw bit low to initiate a software reset (equivalent to pulling rst low). 12 no_busy busy input disable. 0: busy input is active. 1: busy input is disabled. note that this does not affect the busy bit in the general configuration and status register. the busy pin is bidirectional. when enabled, it can be pulled down externally to delay dac updates. 11 dout_on spi dout output disable. dout is disabled by default. 0: dout output disabled. when dout is disabled, the output is pulled low for the duration of the spi frame. 1: dout output enabled. 10 busy global busy status readback. 0: device is busy transferring din code to the dac register. 1: device is not busy. 9:4 reserved. will read back 0. 3:0 rev_id[3:0] device revision
???????????????????????????????????????????????????????????????? maxim integrated products 29 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface applications information power-on reset (por) upon power-on, the output is set to either zero-scale (if m/ z is low) or midscale (if m/ z is high). the entire register map is set to their default values as shown in tables 7 C 11 . power supplies and bypassing considerations for best performance, use a separate supply for the MAX5316. bypass v ddio , avdd_, and avss with high- quality ceramic capacitors to a low-impedance ground as close as possible to the device. a typical high-quality x7r 10 f f capacitor can become self resonant at 2mhz. therefore, it is actually an inductor above 2mhz and is useless for decoupling signals above 2mhz. it is therefore recommended that several capacitors of different values are connected in parallel (e.g. 0.1f || 10f). figure 8 shows the magnitude of impedance of typical 1 f f, 100nf, and 10nf x7r capacitors. as the capacitance reduces, the self-resonant frequency increases. in addition, the parallel combination of all three is shown and exhibits a significant improvement over a single capacitor. these plots do not include any pcb trace inductance. minimize lead lengths to reduce lead inductance. adding just 2nh trace inductance to each of the typical capacitors above produces the effects shown in figure 9 . this shows significant reduction in the self-resonant frequencies of the capacitors. internal linear regulator (bypass) bypass is the output of an internal linear regulator and is used to power digital circuitry. connect bypass to dgnd with a ceramic capacitor in the range of 1 f f to 10 f f with esr in the range of 100m i to 20m i to ensure stability. power-supply sequencing during power-up, ensure that avdd_ comes up before the reference does. if this is not possible, connect a schottky diode between the ref and avdd_ such as the mbr0530t1g. if ref does come up before avdd_, the diode conducts and clamps ref to avdd_. once avdd_ has come up, the diode no longer conducts. ref should always be below avdd_ as specified in the electrical characteristics . avdd_ and avdd_ should be connected together and powered from the same supply. v ddio and avss can be sequenced in any order. always perform a reset operation after all the supplies are brought up to place the device in a known operating state. layout considerations digital and ac transient signals on agnd inputs can create noise at the outputs. connect both agnd inputs to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance (see the force/sense section). use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star con - nect all ground return paths back to agnd. do not use wire-wrapped boards and sockets. use ground plane figure 8. typical x7r capacitor impedance figure 9. typical x7r capacitor impedance with additional 2nh pcb trace inductance 3k 1k 100 10 1 100m 10m 100k 1m 10m 100m 4m impedance (i) frequency (hz) 10nf 1f 100nf 10nf 1f 100nf 3k 1k 100 10 1 100m 10m 100k 1m 10m 100m 4m impedance (i) frequency (hz) 10nf 1f 100nf
???????????????????????????????????????????????????????????????? maxim integrated products 30 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface shielding to improve noise immunity. do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the device package. connect the exposed pad to agnd (analog ground plane). for a recommended layout, consult the MAX5316/ max5318 evaluation kit datasheet. voltage reference selection and layout the voltage reference should be placed close to the dac. the same power-supply decoupling and grounding rules as the dac should be implemented. many voltage refer - ences require an output capacitor for stability or noise reduction. provided the trace between the reference device and the dac is kept short and well shielded, a sin - gle capacitor may be used and placed close to the dac. however, for improved noise immunity, additional capaci - tors may be used but be careful not to exceed the recom - mended capacitance range for the voltage reference. refer to applications note an4300: calculating the error budget in precision digital-to-analog converter (dac) applications for detailed description of voltage refer - ence parameters and trading off the error budget. the max6126 is recommended for 16-bit applications. optimizing data throughput rate the ldac and busy interaction section details the timing of data written to the device and how the dac is updated. data throughput speed can be increased by overlapping the data load time with the busy period and settling time as shown below in figure 10 . following the 24th sclk falling edge, the device holds busy low while transfer - ring the value from the din register to the dac register. providing that the ldac falling edge arrives before the 24th sclk falling edge, and assuming the spi clock fre - quency is high enough, the throughput period is therefore limited by t busy and settling times only. a slight further increase in throughput time can be gained by either tog - gling ldac during the busy period or by pulling it low permanently. however, the exact point at which the dac update occurs is then determined internally as indicated by the busy line rising edge. this is not an exact time. busy line pullup resistor selection the busy pin is an open-drain output. it therefore requires a pullup resistor. a 5.1k i value is recommend - ed as a compromise between power and speed. stray capacitance on this line can easily slow the rise time to an unacceptable level. the busy pin can sink up to 5ma. therefore a resistor as low as v ddio /0.005 may be used if faster rise times are required. figure 10. optimum throughput with stable update period 24th sclk t busy din out busy ldac 24th sclk ldac falling edge before 24th sclk falling edge
???????????????????????????????????????????????????????????????? maxim integrated products 31 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface producing unipolar high-voltage and bipolar outputs figure 11 and figure 12 show how external op amps can be used to produce a unipolar high-voltage output and a bipolar output definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes. this line is drawn between the zero and full-scale codes of the transfer func - tion, once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl is less than or equal to 1 lsb, the dac guarantees no miss - ing codes and is monotonic. offset error offset error indicates how well the actual transfer func - tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after removing the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a ldac high-to-low transition or busy low-to-high transition (whichever occurs last), until the dac output settles to within 0.003% around the final value. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse the glitch impulse occurs at the major carry transitions along the segmented bit boundaries. it is specified as the net area of the glitch impulse which appears at the output when the digital input code changes by 1 lsb. the glitch impulse is specified in nanovolts-seconds (nv-s). digital-to-analog power-up glitch impulse the digital-to-analog power-up glitch is the net area of the glitch impulse which appears at the output when the device exits power-down mode. figure 11. unipolar high-voltage output figure 12. bipolar output ou t 0v to kv ref k = 1 + r2 /r 1 r2 r1 MAX5316 max44251 ou t refo -v re f to v re f r2 r1 = r2 r1 MAX5316 max9632
???????????????????????????????????????????????????????????????? maxim integrated products 32 MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface ordering information chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. +denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. typical operating circuit 2.4v to (v avdd -0.1v) mbr0530t1g vddio 5.1ki 22 ref 0.1f 0.01f 16 c gpio?s spi interface *connect the exposed pad to agnd. 0.1f 1f 10f 2.7v to 5v 1.8v to 5v avdd2 19 avdd1 12 15 refo 13 out 14 rfb bypass 20 linear regulator MAX5316 21 dgnd 11 agnd 17 agnd_s 18 agnd_f 10 avss buffer output buffer 0 to -1.25v 2 busy 23 m/z 8 ts/s b 9 pd 1 rstsel 3 ldac 24 ready 7 cs 6 sclk 5 din 4 dout 0.1f 0.1f 10f 100pf r l interface and control input register dac register 16-bit dac part temp range pin-package MAX5316gtg+ -40 n c to +105 n c 24 tqfn-ep* package type package code outline no. land pattern no. 24 tqfn-ep t2445+1 21-0201 90-0083
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 33 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/12 initial release MAX5316 16-bit, 1 lsb accuracy voltage output dac with spi interface

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